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Allwinner /D1H /UART[2] /RXDMA_LMT

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Interpret as RXDMA_LMT

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https://regviz.com/r/Allwinner/D1H/UART[5]/RXDMA_LMT#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0limit_size

Description

UART RXDMA Limit Register

Fields

limit_size

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data